Integrated circuits are formed by depositing several layers of different materials. As each layer is deposited, it is patterned according to the function for which the layer is designed. For example, a layer that is designed to be part of an electrical interconnect system may be formed of a metal based compound. The layer of metal based compound may then be etched to form patterns of contact areas which are joined by leads.
The pattern in which a layer is to be formed is often created by a photolithographic process. In a typical method, the deposited layer is coated with a polymer based photoresist. A mask, having the image of the pattern desired, is placed in proximity to the photoresist covered layer. The image from the mask is transferred to the photoresist by irradiating the areas of the photoresist which are not covered by the pattern in the mask. After irradiation, the photoresist is developed, and portions of the photoresist are washed away, as defined by the pattern in the mask. Thus, certain areas of the layer to be patterned are covered with photoresist, and other areas of the layer are exposed.
The exposed areas of the layer can be removed by using either a wet or dry etch. A wet etch is typically done with a water based solution that reacts with and removes those portions of the layer not protected by the photoresist. A dry etch may be done by sputtering either an inert gas, or a gas which reacts with the material of the layer, against the layer. Etching wears the exposed areas of the layer away, while leaving intact those areas of the layer protected by the photoresist. In this manner the pattern is transferred from the mask, to the photoresist, and then finally to the layer itself.
Once the layer is patterned, the photoresist is usually removed, to prepare the integrated circuit for the deposition of additional layers, or other subsequent processing. It is important that as much of the photoresist as possible be removed prior to subsequent processing. If some photoresist is left intact on the surface of a layer, it may interfere with the proper operation of the finished integrated circuit. For example, if a second metal layer were to be deposited on top of a first metal layer, photoresist remaining on the first metal layer may create an open circuit in areas where the two layers were intended to make ohmic contact.
The photoresist may be removed by use of an aqueous solution, either alone or in combination with physical scrubbing or pulsed jets. However, the aqueous based solutions, and other methods of photoresist removal, tend to induce the formation of oxides, such as silicon oxide, on the exposed surfaces of the integrated circuit. Oxides on the surface of a layer can create the same types of problems as described above for the photoresist. Therefore, before a subsequent layer of the integrated circuit is deposited, the previously deposited and patterned layer should be free of undesirable material, such as the oxides and polymeric photoresist, and other solutions.
The integrated circuit may be plasma cleaned with an inert gas, such as argon, to remove the undesirable material. The energized argon ions created by the plasma tend to physically bombard the material on the integrated circuit, dislodging it in a manner such that it can be pumped away in a gaseous state. The relatively flat areas of the integrated circuit are not excessively difficult to adequately clean in this manner.
However, the recessed areas of the integrated circuit, such as vias, are more difficult to clean. This is especially true as the geometry of integrated circuits has shrunk. The reduction in device geometry has typically resulted in an increase in the aspect ratio of topographical features, such as vias. The aspect ratio of a feature is the depth of the feature divided by the width of the feature. Thus, as the aspect ratio increases, it is an indication that the depth of the feature is increasing in proportion to the width of the feature.
It has become increasingly difficult to adequately remove material from the relatively deeper, narrower vias required by newer generation integrated circuits. The reason for this is that the material dislodged by the argon at the bottom of a high aspect ratio via tends to redeposit on the side walls of the via before it can escape the deep, narrow via. The material may also redeposit on the flatter areas of the integrated circuit. This creates problems with the integrated circuit during subsequent processing and use.
What is needed, therefore, is a method of removing undesirable material, such as oxides and polymers, from integrated circuits having high aspect ratio topographical features, in a manner such that the material is not redeposited on the integrated circuit.